FPGA-playground

A notebook of Verilog exercises, all running on an Olimex iCE40HX8K-EVB. Simple designs like button-to-LED sit alongside worked HDLBits practice, each with a testbench, AIG and netlist diagrams.

What's in the repo

• Verilog designs like but-2-led and its clocked and blocking/non-blocking variants.
• HDLBits practice modules (adders, shift registers, case statements).
• Testbenches per design.
• Generated AIG and netlist SVGs.

The flow

Each design is Verilog plus a `.pcf` pin map. APIO synthesizes with the iCE40 toolchain, and scripts render the AIG and netlist to SVG with graphviz and netlistsvg. The bitstream reaches the board through a reprogrammed FT2232H. I flashed that chip with the iCEstick EEPROM so APIO would recognize it as a programmer.