RISC-V emulator

RISC-V instructions running on an 8-bit AVR. That is the point. This is an RV32 CPU emulator in plain C, written to understand RISC-V by emulating it. It passes the official riscv-arch-test suite for the core extensions. No architecture-specific code, so the same library runs on an ATSAMD21 and x86-64 Linux.

The code

• One library, no CPU dependencies.
• RV32I plus extensions M, A, C and the B bit-manipulation subsets.
• A config header toggling which extensions get compiled in.
• The memory and syscall hooks are yours to write.

Inside the loop

Programs run inside a loop you drive yourself. Call RiscvEmulatorLoop() over and over, each time handing it the next instruction. Decoding is two-pass. A switch() on the opcode picks the group, then a nested switch() decodes and executes. Bitfield structs unpack the fields, with a union of helper structs when bits need untangling. Your side just supplies RAM and the memory and syscall callbacks.