RISC-V-emulator-Native

The emulator, compiled as a normal program. Instead of sitting on a microcontroller, my RISC-V emulator builds as a native executable that RISCOF runs as the device under test.

Pieces

• A PlatformIO Native build config.
• The emulator core.
• A memory shim.
• The `hook.c` extension point.
• A script that generates ISA-extension combination build environments.

The run

The binary reads `dut-rom.bin` and `dut-ram.bin`, loads the RAM defaults, and emulates until a signature window or loop limit stops it. It writes `dut-ram-after.bin` for RISCOF to compare. I build one binary per ISA-extension combination so the tests match exactly what the emulator claims.