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RISC-V-emulator-RISCOF

My try at running the riscv-arch-test using RISCOF against my RISC-V emulator.

RISC-V-emulator-RISCOF

⭐1Python

My try at running the riscv-arch-test using RISCOF against my RISC-V emulator.

RISC-V-emulator-RISCOF

This is my harness for running the official RISC-V architecture tests against my own emulator. It adapts the emulator to RISCOF via a Python plugin, letting the same test suite used for real cores check a hobby project's correctness.

Pieces

  • `rve/rve_isa.yaml` describes the supported ISA, `rve/riscof_rve.py` bridges to RISCOF, and `runtests.sh` runs the whole suite
  • SAIL reference config lives under `sail_cSim/`

The compare step

The framework compiles each test, runs it on the emulator, and reruns it on the SAIL reference simulator. It compares the two memory signatures. A difference means the emulator deviates.

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